Flash memory devices (e.g., NAND, NOR, etc.) have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use one-transistor memory cells. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. For example, a row of memory cells might be those memory cells commonly connected to an access line. Columns of the array might include strings (often termed NAND strings) of memory cells connected together in series between a pair of select transistors, e.g., a source select transistor and a drain select transistor. Each source select transistor is connected to a source, while each drain select transistor is connected to a data line, such as bit line. For example, as used herein when elements are connected they are electrically connected, e.g., by means of an electrically conductive path. As used herein, when elements are disconnected, for example, they are electrically disconnected (e.g., electrically isolated) from each other.
A “column” may refer to memory cells that are commonly connected to a data line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. Note, for example, that for an array having a plurality of memory blocks, a string of memory cells of each memory block might be selectively connected to a common data line through a drain select transistor.
A row of memory cells can, but need not, include all memory cells commonly connected to an access line. A row of memory cells might include every other memory cell commonly connected to an access line. For example, memory cells commonly connected to an access line and selectively connected to even data lines may be a row of memory cells, while memory cells commonly connected to that access line and selectively connected to odd data lines may be another row of memory cells. Other groupings of memory cells commonly connected to an access line may also define a row of memory cells. For certain memory devices, all memory cells commonly connected to a given access line might be deemed a physical row, while those portions of the physical row that are read during a single read operation or programmed during a single program operation (e.g., even or odd memory cells) might be deemed a logical row, sometimes referred to as a page.
Some memory devices might include stacked memory arrays, e.g., often referred to as three-dimensional memory arrays. For example, a stacked memory array might include a plurality of vertical strings (e.g., NAND strings) of memory cells, e.g., connected in series, between a source and a data line. The term vertical may be defined, for example, as a direction that is perpendicular to a base structure, such as a surface of an integrated circuit die. It should be recognized the term vertical takes into account variations from “exactly” vertical due to routine manufacturing and/or assembly variations and that one of ordinary skill in the art would know what is meant by the term vertical.
Memory cells, such as non-volatile memory cells, can be programmed to have a single bit, e.g., during single-level programming, or multiple bits, e.g., during multilevel programming. For example, memory cells programmed to have a single bit may sometimes be referred to as single-level cells (e.g., SLCs), and memory cells programmed to have multiple bits may sometimes be referred to as multilevel cells (e.g., MLCs).
A respective data value (e.g., as represented by a bit pattern) may be assigned to each of a plurality of levels, where each level corresponds to a respective data state. That is, for example, a bit pattern of K bits might be assigned to each of the 2K program levels, where K might be an integer greater than or equal to one (1).
For single-bit-per cell programing, for example, K may be 1, and thus a single bit may be assigned to each of the two program levels, e.g., where each of the two program levels corresponds to a distinct range of threshold voltages (Vts). For example, a single-bit (e.g., two-level) cell might be assigned a bit value of 1 when it is at its lowest program level, corresponding to a range of Vts, e.g. that might be an erased data state, and might be assigned a bit value of zero (0) when it is at its highest program level, corresponding to another range of Vts, e.g., that might be referred to as a programmed data state.
For multi-bit-per-cell programming (e.g., K greater than 1), for example, each level (e.g., data state) may be characterized by a corresponding distinct range of threshold voltages (Vts) of a plurality of distinct ranges of threshold voltages that can be stored on the multilevel memory cells. A margin (e.g., a certain number of volts), such as a dead space, may separate adjacent threshold-voltage ranges, e.g., to facilitate differentiating between data values. This technology permits the storage of two or more bits per memory cell.
A page buffer, for example, might be connected to a data line that is selectively connected to a memory cell, such as a target memory cell targeted for programming during a program operation or sensing, e.g., during a read operation. In some examples, there may be a page buffer for each of the bits assigned to a multi-bit-per-cell memory cell. That is, for example, for a K-bit memory cell there might be N=K page buffers.
Some memory devices, for example, might be configured to program memory cells to have different numbers of bits. For example, a target memory cell might be assigned K bits, e.g., while a memory device is operating in one mode, and the target memory cell might be assigned fewer than K bits, e.g., while operating in another mode. For example, when K bits are assigned to the target memory cell all N=K page buffers may be used, but when fewer than K bits are assigned to the target memory cell fewer than N=K page buffers may be used.
In some examples, memory cells might be used to store two bits per cell (e.g., K=2) when a memory device is operating in a two-bit-per-cell (e.g., a four-level) mode. For example, there might be two page buffers connected to the data line that is selectively connected to the target memory cell, one page buffer for each of the two bits. However, when the memory device is operating in a single-bit-per-cell mode (K=1), the target memory cells might be used to store a single bit, and only one of the two buffers might be used for the single bit, while the other of the two buffers might not be used.